[Hackrf-dev] HackRF: MAX5864 -> MAX2837 differential pair connections

[Frank Liu]

Hey folks,

I was flipping through the HackRF schematic when I noticed that the TX
differential pairs between the MAX5864 and MAX2837 seem to be reversed,
i.e. TXBBI- of the MAX2837 is connected to ID+ of the MAX5864 and vice
versa. The same goes for the Q data stream (and for the receive path).

I assume this was done on purpose. What is the reasoning behind this?

Thanks,
Frank

[Dominic Spill]

Post by Frank Liu
I was flipping through the HackRF schematic when I noticed that the TX

differential pairs between the MAX5864 and MAX2837 seem to be reversed,
i.e. TXBBI- of the MAX2837 is connected to ID+ of the MAX5864 and vice
versa. The same goes for the Q data stream (and for the receive path).

Post by Frank Liu
I assume this was done on purpose. What is the reasoning behind this?

Yes, this was intentional. If you look at the layout of the board, the
pins are in different orders on the two parts, so routing them would
involve crossing the signals, and using vias to move them on to different
board layers. All of this is a negative when it comes to signal integrity.

As they are differential signals, we can switch them as long as we correct
the values in the digital domain, which we do in the CPLD here:
https://github.com/mossmann/hackrf/blob/master/firmware/cpld/sgpio_if/top.vhd#L117

I hope this explanation helps and was clear enough, I'm definitely not one
of the hardware people on this project, so this was pieced together from
what I've learned from Mike, Jared, and others.

Thanks,
Dominic

[Frank Liu]

Hey Dominic,

Thanks for the reply. Makes sense now when I look at the design files and
CPLD code.

Forgive me for playing devil's advocate - I'm relatively new to PCB design
and just trying to understand as much as I can - but I couldn't help but
notice that the some of the clock signals traverse the bottom layer,
despite having much higher component frequencies than baseband analog
signals due to the short rise and fall times of CMOS clock outputs. Was
this an oversight or purposely left in due to the inherent noisy nature of
digital logic?

Best,
Frank

Post by Frank Liu

Post by Frank Liu
I was flipping through the HackRF schematic when I noticed that the TX

differential pairs between the MAX5864 and MAX2837 seem to be reversed,
i.e. TXBBI- of the MAX2837 is connected to ID+ of the MAX5864 and vice
versa. The same goes for the Q data stream (and for the receive path).

Post by Frank Liu
I assume this was done on purpose. What is the reasoning behind this?

Yes, this was intentional. If you look at the layout of the board, the
pins are in different orders on the two parts, so routing them would
involve crossing the signals, and using vias to move them on to different
board layers. All of this is a negative when it comes to signal integrity.
As they are differential signals, we can switch them as long as we correct
https://github.com/mossmann/hackrf/blob/master/firmware/
cpld/sgpio_if/top.vhd#L117
I hope this explanation helps and was clear enough, I'm definitely not one
of the hardware people on this project, so this was pieced together from
what I've learned from Mike, Jared, and others.
Thanks,
Dominic